source: Carnegie Mellon Computer Architecture 2014年1月18日
Lecture videos from CMU 18-447, Computer Architecture, in Spring 2014.
Prof. Onur Mutlu (http://users.ece.cmu.edu/~omutlu/)
Course webpage: http://www.ece.cmu.edu/~ece447/s14/do...
Module materials: http://www.ece.cmu.edu/~ece447/s14/do...
Lecture 1. Introduction and Basics 1:41:39
Lecture 2. Fundamental Concepts and ISA 1:43:31
Lecture 3. ISA Tradeoffs 1:44:49
Lecture 4. ISA Tradeoffs (cont.) 1:44:50
Lecture 5. Single-Cycle and Multi-Cycle uArch 1:25:33
Lecture 6. Multi-Cycle and Microprogrammed uArch 1:44:37
Course webpage: http://www.ece.cmu.edu/~ece447/s14/do...
Module materials: http://www.ece.cmu.edu/~ece447/s14/do...
Lecture 1. Introduction and Basics 1:41:39
Lecture 2. Fundamental Concepts and ISA 1:43:31
Lecture 3. ISA Tradeoffs 1:44:49
Lecture 4. ISA Tradeoffs (cont.) 1:44:50
Lecture 5. Single-Cycle and Multi-Cycle uArch 1:25:33
Lecture 6. Multi-Cycle and Microprogrammed uArch 1:44:37
Lecture 7. Pipelining 1:35:53
[deleted video]
Lecture 9. Branch Handling and Branch Prediction 1:35:05
Lecture 10. Branch Handling & Branch Prediction II (part 2) 36:05
Lecture 10. Branch Handling & Branch Prediction II (part 1) 1:02:23
Lecture 11. Precise Exceptions 1:39:15
Lecture 12. Virtual Memory I 1:25:42
Lecture 13. Virtual Memory II 1:06:48
Lecture 14. Out-of-order Execution 1:49:52
Lecture 15. Load/Store Handling and Data Flow 1:26:25
Lecture 16. SIMD Processing (Vector Processors) 1:39:18
Lecture 17. GPUs, VLIW, Systolic Arrays 1:43:21
Lecture 19. Memory Hierarchy and Caches 1:40:09
Lecture 20. Better Caching 1:16:34
Lecture 21. Advanced Caching and MLP 1:37:30
Lecture 24. Memory Scheduling 1:42:19
Lecture 25. Main Memory Wrap-Up 1:42:19
Lecture 26. Runahead Execution 1:38:16
Lecture 27. Prefetching 1:43:00
Lecture 28. Multiprocessors 1:35:59
Lecture 29. Consistency & Coherence 1:45:30
Midterm II Review Session 1:18:31
Lecture 31. Interconnection Networks 1:42:27
Lecture 32. Asymmetric Multi-Core 1:38:56
Lecture 33. Emerging Memory Tech 1:04:40
[deleted video]
Lecture 9. Branch Handling and Branch Prediction 1:35:05
Lecture 10. Branch Handling & Branch Prediction II (part 2) 36:05
Lecture 10. Branch Handling & Branch Prediction II (part 1) 1:02:23
Lecture 11. Precise Exceptions 1:39:15
Lecture 12. Virtual Memory I 1:25:42
Lecture 13. Virtual Memory II 1:06:48
Lecture 14. Out-of-order Execution 1:49:52
Lecture 15. Load/Store Handling and Data Flow 1:26:25
Lecture 16. SIMD Processing (Vector Processors) 1:39:18
Lecture 17. GPUs, VLIW, Systolic Arrays 1:43:21
Lecture 19. Memory Hierarchy and Caches 1:40:09
Lecture 20. Better Caching 1:16:34
Lecture 21. Advanced Caching and MLP 1:37:30
Lecture 24. Memory Scheduling 1:42:19
Lecture 25. Main Memory Wrap-Up 1:42:19
Lecture 26. Runahead Execution 1:38:16
Lecture 27. Prefetching 1:43:00
Lecture 28. Multiprocessors 1:35:59
Lecture 29. Consistency & Coherence 1:45:30
Midterm II Review Session 1:18:31
Lecture 31. Interconnection Networks 1:42:27
Lecture 32. Asymmetric Multi-Core 1:38:56
Lecture 33. Emerging Memory Tech 1:04:40
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