Computer Architecture (Fall 2013) by Onur Mutlu at Carnegie Mellon University

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source: Carnegie Mellon Computer Architecture    2013年8月31日
Fall 2013 - 740 Computer Architecture - Carnegie Mellon
Lecturer: Prof. Onur Mutlu (http://users.ece.cmu.edu/~omutlu/)
Course webpage: http://www.ece.cmu.edu/~ece740/f13/do...
Module materials: http://www.ece.cmu.edu/~ece740/f13/do...

Module 0.1 - Introduction 42:33
Module 0.2 - Grading and Policies 4:45
Module 0.3 - Paper Reviews 9:14
Module 0.4 - First Assignments 10:54
Module 0.5 - Project Proposal 27:02
Module 1.1 - Parallel Basics 1:13:08
Module 1.2 - Task Assignment 46:11
Module 1.3 - Multi Core Why 1:26:22
Module 1.4 - Multi Core Evolution 1:34:40
Module 2.1 - Asymmetry 2:04:41
Lecture 3 - Programming Models 1:18:11
Module 2.3 - Memory Consistency 1:26:59
Module 2.4 - Cache Coherence 2:08:45
Module 2.5 - Speculation (1 of 4) 31:50
Module 2.5 - Speculation (2 of 4) 1:19:46
Module 2.5 - Speculation (3 of 4) 20:17
Module 2.5 - Speculation (4 of 4)  1:14:45
Lecture 16 - Virtual Memory 1 1:06:51
Lecture 17 - Virtual Memory 2 56:20
Lecture 23 - Caches  1:37:44
Lecture 18 - Virtual Memory 3 1:12:19
Lecture 22 - Memory Hierarchy 1:45:35
Lecture 24 - Advanced Caches  1:40:55
Module 3.4 - Shared Caches (1 of 6) 17:33
Module 3.4 - Shared Caches (2 of 6) 27:28
Module 3.4 - Shared Caches (3 of 6) 31:11
Module 3.4 - Shared Caches (4 of 6) 31:06
Module 3.4 - Shared Caches (5 of 6) 17:09
Module 3.4 - Shared Caches (6 of 6) 43:06
Module 3.5 - Main Memory (1 of 7) 21:21
Module 3.5 - Main Memory (2 of 7) 56:50
Module 3.5 - Main Memory (3 of 7)  24:36
Module 3.5 - Main Memory (4 of 7) 26:06
Module 3.5 - Main Memory (5 of 7) 21:50
Module 3.5 - Main Memory (6 of 7)  24:25
Module 3.5 - Main Memory (7 of 7) 18:22
Module 3.6 - Emerging Mem Tech (1) 34:00
Module 3.6 - Emerging Mem Tech (2)  45:48
Guest Lecture - Self Repairing Arch 1:36:21
Module 3.7 - Mem. Interference (1) 1:22:22
Module 3.7 - Mem. Interference (2) 1:17:15
Onur Mutlu at Bogazici University, "Memory QoS" Lecture 2.3 (part 4) 46:20
Module 4.1 - Interconnects I 1:25:38
Module 4.2 - Interconnects II 1:49:39
Lecture 15 - Data Flow and SIMD 1:46:25
Lecture 19 - SIMD and GPUs 1:43:24
Lecture 20 - GPUs, VLIW, Systolic Arrays 1:46:41
Parallel Computer Architecture 2012- Lec 22 - Dataflow I 1:25:01
Parallel Computer Architecture 2013 - Lec. 23-Dataflow II 54:59
Lecture 20 - GPUs, VLIW, Systolic Arrays 1:46:41
Parallel Computer Architecture 2013 - Lec 9 - Multithreading 1:35:45
Parallel Computer Architecture 2012 - Lecture 10 - Multithreading II 1:33:10
Parallel Computer Architecture 2013 - Lec 13-Multi-threading II 1:37:14
Parallel Computer Architecture 2013 - Lec 15 - Speculation 1 1:38:31
Lecture 14 - Out-of-Order Execution 1:48:34
Lecture 15 - Data Flow and SIMD  1:46:25
Lecture 21 Static Instruction Scheduling 1:50:04
Lecture 11 - Branch Prediction  1:43:34
Lecture 12 - Predication and Exceptions 1:44:14
Lecture 28 - Runahead Execution 1:37:31