Digital System design with PLDs and FPGAs by Kuruvilla Varghese (IISc Bangalore)

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source: nptelhrd    2014年9月2日
Electronics - Digital System design with PLDs and FPGAs by Prof. Kuruvilla Varghese, Department of Electronics & Communication Engineering, IISc Bangalore. For more details on NPTEL visit http://nptel.ac.in.

01 Course Contents, Objective 57:34
02 Revision of Prerequisite 59:34
03 Design of Synchronous Sequential Circuits 52:35
04 Analysis of Synchronous Sequential Circuits 57:18
05 Top-down Design 57:54
06 Controller Design 58:40
07 Control algorithm and State diagram 56:49
08 Case study 1 58:24
09 Entity, Architecture and Operators 58:16
10 Concurrency, Data flow and Behavioural models 57:22
11 Structural Model, Simulation 59:14
12 Simulating Concurrency 59:06
13 Classes and Data types 57:38
14 Concurrent statements and Sequential statements 57:56
15 Sequential statements and Loops 59:29
16 Modelling flip-flops, Registers 57:14
17 Synthesis of Sequential circuits 57:59
18 Libraries and Packages 56:54
19 Operators, Delay modelling 57:28
20 Delay modelling 58:44
21 VHDL Examples 58:22
22 VHDL Examples, FSM Clock 59:00
23 FSM issues 1 52:16
24 FSM Issues 2 57:51
25 FSM Issues 3 58:07
26 VHDL coding of FSM 58:43
27 FSM Issues 4 59:12
28 FSM Issues 5 58:11
29 Synchronization 1 59:03
30 Synchronization 2 58:15
31 Evolution of PLDs 58:38
32 Simple PLDs 59:17
33 Simple PLDs: Fitting 59:11
34 Complex PLDs 58:24
35 FPGA Introduction 58:29
36 FPGA Interconnection, Design Methodology 58:20
37 Xilinx Virtex FPGA’s CLB 58:51
38 Xilinx Virtex Resource Mapping, IO Block 58:44
39 Xilinx Virtex Clock Tree 57:47
40 FPGA Configuration 58:30
41 Altera and Actel FPGAs 58:42
42 VHDL Test bench 58:34
43 Case study 2 58:05
44 Case study on FPGA Board 57:19