Design Verification & Test of Digital VLSI Circuits by Jatindra Kumar Deka & Santosh Biswas (IIT Guwahati)

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source: nptelhrd   2013年2月14日
Computer-Design Verification & Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT Guwahati. For more details on NPTEL visit http://nptel.iitm.ac.in

Mod-01 Lec-01 Introduction to Digital VLSI Design Flow 1:11:21
Mod-01 Lec-02 High Level Design Representation 57:35
Mod-01 Lec-03 Transformations for High Level Synthesis 57:37
Mod-02 Lec-01 Introduction to HLS: Scheduling, Allocation and Binding Problem 1:01:16
Mod-02 Lec-02 Scheduling Algorithms-1 57:38
Mod-02 Lec-03 Scheduling Algorithms-2 1:10:10
Mod-02 Lec-04 Binding and Allocation Algorithms 1:07:01
Mod-03 Lec-01 Two level Boolean Logic Synthesis-1 1:08:11
Mod-03 Lec-02 Two level Boolean Logic Synthesis-2 1:04:16
Mod-03 Lec-03 Two level Boolean Logic Synthesis-3 1:23:50
Mod-03 Lec-04 Heuristic Minimization of Two-Level Circuits 1:16:37
Mod-03 Lec-05 Finite State Machine Synthesis 1:13:42
Mod-03 Lec-06 Multilevel Implementation 1:03:52
Mod-04 Lec-01 Introduction to formal methods for design verification 53:09
Mod-04 Lec-02 Temporal Logic: Introduction and Basic Operators 55:20
Mod-04 Lec-03 Syntax and Semantics of CTL 59:34
Mod-04 Lec-04 Syntax and Semantics of CTL -- Continued 1:08:58
Mod-04 Lec-05 Equivalence between CTL Formulas 1:00:35
Mod-05 Lec-01 Introduction to Model Checking 1:02:56
Mod-05 Lec-02 Model Checking Algorithms I 55:36
Mod-05 Lec-03 Model Checking Algorithms II 56:45
Mod-05 Lec-04 Model Checking with Fairness 57:27
Mod-06 Lec-01 Binary Decision Diagram: Introduction and construction 1:03:22
Mod-06 Lec-02 Ordered Binary Decision Diagram 1:01:43
Mod-06 Lec-03 Operation on Ordered Binary Decision Diagram 1:00:53
Mod-06 Lec-04 Ordered Binary Decision Diagram for State Transition Systems 1:01:14
Mod-06 Lec-05 Symbolic Model Checking 1:01:51
Mod-07 Lec-01 Introduction to Digital VLSI Testing 54:46
Mod-07 Lec-02 Functional and Structural Testing 1:00:21
Mod-07 Lec-03 Fault Equivalence 57:13
Mod-08 Lec-01 Fault Simulation-1 52:25
Mod-08 Lec-02 Fault Simulation-2 1:02:11
Mod-08 Lec-03 Fault Simulation-3  1:08:10
Mod-08 Lec-04 Testability Measures (SCOAP) 59:51
Mod-09 Lec-01 Introduction to Automatic Test Pattern Generation (ATPG) and ATPG Algebras 54:35
Mod-09 Lec-02 D-Algorithm-1 56:43
Mod-09 Lec-03 D-Algorithm-2 1:05:33
Mod-10 Lec-01 ATPG for Synchronous Sequential Circuits 1:09:08
Mod-10 Lec-02 Scan Chain based Sequential Circuit Testing-1 52:45
Mod-10 Lec-03 Scan Chain based Sequential Circuit Testing-2 52:11
Mod-11 Lec-01 Built in Self Test-1 59:46
Mod-11 Lec-02 Built in Self Test-2 54:19
Mod-11 Lec-03 Memory Testing-1 57:07
Mod-11 Lec-04 Memory Testing-2 1:12:39

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